ENGR857

Homework # 3 Due: Nov 28th

Building FPGAs (cont'd)( Copyright: materails borrowed from Russell Tessier at University of Massachusetts)

6 Connection Box Flexibility

In this section you will evaluate the effect of connection block flexibility on transistor count. This will be accomplished by rerunning the VPR router and trans count with different Fc settings using the same placements found in the previous exercise

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Ex 4: Changing connection block flexibility

Rerun the above experiments for pdc and apex2 for N = 1, I = 4, this time with Fc = 0.6 and Fc = 0.8. Start from the previously determined .p placement files and rerun the VPR router and trans count. Note: Before doing the experiments make sure Fc input and Fc output in file vpr/4lut sanitized.arch and Fc in the local makefile (eg tests/apex2/Makefile) have all been set to the correct value (either 0.6 or 0.8). Summarize your results in a short paragraph and table including values for Fc = 1 found in the previous exercise. The table should include the number of transistors needed to implement the whole device in addition to the number of transistors per logic cluster.

Ex 5: Changing connection block flexibility

Rerun the above experiments for pdc and apex2 for N = 4, I = 10, this time with Fc of 0.3 and 0.7. Be sure to follow the same procedure as the previous exercise regarding modifying files except note that vpr/4x4lut sanitized.arch should be used. Summarize your results in a short paragraph and table including values for Fc = 0.5 found previously. The table should include the number of transistors needed to implement the whole device in addition to the number of transistors per logic cluster.

7 Switchbox and Intra-Cluster Flexibility

In this section you have the opportunity to evaluate the effect of switchboxflex ibility on FPGA array area for switchboxes that contain both pass gates and tri-state buffers.

Ex 6: Transistor counts for switchboxes

How many transistors are needed to implement a switchboxwith 2 inputs per side and with Fs = 3 and Fs = 4 if pass transistors are used for connections. How does the value change if bidirectional tri-state buffers are used? Note Figure 4 in [5] and Figure 9 in [4] for ideas regarding buffer count and transistors per multiplexer. How many transistors are needed to implement a directional switch boxwith Fs = 3 and two I/Os per side (note Figure 4 in [3]). Create a table to summarize your results and rank the possible implementations for performance.

Ex 7: FPGAIn tra-cluster Multiplexer size

How many transistors are needed to implement a LUT input multiplexer similar to the ones shown in Figure 2 as a function of N, I, and K?

8 FPGA Architecture

In this section you will comment on the results of Ahmed and Rose [1] in terms of FPGA area and delay.

Ex 8: FPGAA rea Tradeoffs

Briefly describe some of the factors which lead to the area curve shapes in Figures 7 and 8 of [1]. Summarize your arguments in a few paragraphs.

Ex 9: FPGADela y Tradeoffs

Briefly describe some of the factors which lead to the delay curve shapes in Figure 14 of [1]. Summarize your arguments in a few paragraphs.

References

[1] E. Ahmed and J. Rose. The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density. IEEE Transactions on VLSI, Mar. 2004.
[2] V. Betz and J. Rose. Cluster-based Logic Block for FPGAs: Area-Efficiency vs. Input Sharing and Size. In Proceedings, Custom Integrated Circuits Conference, 1997.
[3] G. Lemieux, E. Lee, M. Tom, and A. Yu. Directional and Single-driver Wires in FPGA Interconnect. In IEEE International Conference on Field Programmable Technology, Brisbane, Australia, Dec. 2004.
[4] D. Lewis. The StratixI I Logic and Routing Architecture. In International Symposium on Field Programmable Gate Arrays, Monterey, Ca., Feb. 2005.
[5] A. Marquardt, V. Betz, and J. Rose. Using Cluster-Based Logic Blocks and Timingdriven Packing to Improve FPGA Speed and Density. In International Symposium on Field Programmable Gate Arrays, Monterey, Ca., Feb. 1999.