VLSI Research Lab

Publications:

1. H. Mahmoodi, V. Mohan, M. Cooke, and K. Roy, “Ultra Low Power Clocking Scheme Using Energy Recovery and Clock Gating," accepted for IEEE Transactions on Very Large Scale Integration Systems
2. V. Mohan and H. Mahmoodi, “Clock Gating and Negative Edge Triggering for Energy Recovery Clock,” IEEE International Symposium on Circuits and Systems, pp. 1141-1144, May 2007
3. R. Kuchipudi and H. Mahmoodi, “Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS,” IEEE International Symposium on Quality Electronic Design, pp. 27-32, Mar. 2007
4. J. Yeung and H. Mahmoodi, “Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies,” IEEE International Systems-On-Chip Conference, pp. 261-264, Sep. 2006