Hamid Mahmoodi

Welcome!

Research :: Courses :: Papers and Publications :: Professional Associations :: CV

Research Interests ::

• Design solutions for emerging nanotechnologies
• Design for reliability in nano-scale technologies
• Low-power, robust, and high-performance design in nano-scale technologies
• Low-power VLSI testing and design for testability
• Very Large Scale Integrated (VLSI) circuits and systems

Visit Nano-electronics and Computing Research Center (NeCRC) for more details on my research acitvities.

Courses ::

• ENGR 856: Nano-Scale Circuits and Systems
• ENGR 852: Advanced Digital Design
• ENGR 848: Digital VLSI Design
• ENGR 453: Digital Integrated Circuit Design
• ENGR 378: Digital System Design
• ENGR 356: Basic Computer Architecture

Papers and Publications ::

IEEE has copyright on papers published in IEEE journals and conferences. IEEE papers are available in IEEE Xplore Digital Library.

Refereed Journal Papers:

• S. Paul, H. Mahmoodi, and S. Bhunia, “Low-Overhead Fmax Calibration at Multiple Operating Points Using Delay Sensitive Based Path Selection,” accepted for ACM Transactions on Design Automation of Electronic Systems
• H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, “Ultra Low Power Clocking Scheme Using Energy Recovery and Clock Gating," IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 1, pp. 33-44, Jan 2009
• Y. Wang, H. Mahmoodi, L-Y. Chiou, H. Choo, J. Park, W. Jeong, and K. Roy, “Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering,” Journal of Signal Processing Systems, Dec. 2008
• S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, "Arbitrary Two-Pattern Delay Testing Using A Low-Overhead Supply Gating," Journal of Electronic Testing Theory and Applications, June 2008
• K. Kim, H. Mahmoodi, and K. Roy, “A Low-Power SRAM Using Bit-Line Charge-Recycling,” IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 446-458, Feb. 2008
• S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Reduction of Parametric Failures in Sub-100nm SRAM Array using Body Bias," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 174-183, Jan. 2008
• A. Datta, A. Goel, T. Cakici, H. Mahmoodi, D. Lekshmanan, and K. Roy, “Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 1957-1966, Nov. 2007
• S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, “Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 6, pp. 1370-1382, June 2007
• N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy, "A Novel Low-Overhead Operand Isolation Technique for Low-Power Datapath Synthesis," IEEE Transactions on Very Large Scale Integration Systems, vol. 14, no. 9, pp. 1034-1039, Sep. 2006
• S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "A Novel High Performance and Robust Sense Amplifier Using Independent Gate Control in Sub-50nm Double-Gate MOSFET," IEEE Transactions on Very Large Scale Integration Systems, vol. 14, no. 2, pp. 183-192, Feb. 2006
• Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, “Efficient Testing of SRAM with Optimized March Sequences and a Novel DFT Technique for Emerging Failures due to Process Variations,” IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 11, pp. 1286-1295, Nov. 2005
• H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "Estimation of Delay Variations Due to Random-Dopant Fluctuations in Nanoscale CMOS Circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1787-1796, Sep. 2005
• S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nano-Scaled CMOS," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 12, pp. 1859-1880, Dec. 2005
• S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, "Low-Power Scan Design Using First Level Supply Gating," IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 3, pp. 384-395, Mar. 2005
• A. Agrawal, B. Paul, H. Mahmoodi, A. Datta, and K. Roy, "A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies," IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 1, pp. 27-38, Jan. 2005
• H. Mahmoodi and K. Roy, “Diode-Footed Domino: A Leakage-Tolerant High Fan-in Dynamic Circuit Design Style,” IEEE Transactions on Circuits and Systems I, vol. 51, no. 3, pp. 495–503, Mar. 2004
• J. Park, W. Jeong, H. Mahmoodi, Y. Wang, H. Choo, and K. Roy “Computation Sharing Programmable FIR Filter for Low Power and High Performance Applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 2, pp. 348–357, Feb. 2004
• K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003
• K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakage current in deep-submicron CMOS circuits,” Journal of Circuits, Systems, and Computers, vol. 11, no. 6, pp. 575-600, Dec. 2002
• H. Mahmoodi, A. Afzali-Kusha, and M. Nourani “An adiabatic carry-look ahead adder with efficient supply clock generator,” IEE Proceedings on Circuits, Devices and Systems, vol. 148, no. 5, pp. 229-234, Oct 2001

• F. Moradi, D. Wisland, and H. Mahmoodi, “New SRAM Design Using Body Bias Technique for Ultra Low Power Applications,” accepted for IEEE International Symposium on Quality Electronic Design, Mar. 2010
• F. Moradi, D. Wisland, and H. Mahmoodi, “Improved Write Margin 6T-SRAM for Low Power Applications,” IEEE International System-On-Chip Conference, Sep. 2009
• E. Lyons, V. Ganti, R. Goldman, V. Melikyan, and H. Mahmoodi, “Full-Custom Design Project for Digital VLSI and IC Design Courses using Synopsys Generic 90nm CMOS Library,” International Conference on Microelectronic Systems Education, pp. 45-48, July 2009
• F. Moradi, D. Wisland, H. Mahmoodi, T. V. Cao, and M. Zarre Dooghabadi, “Adaptive Supply Voltage Circuit using Body Biasing Technique,” International Conference on Mixed Design of Integrated Circuits and Systems, pp. 215-219, June 2009
• F. Moradi, D. T. Wisland, H. Mahmoodi, S. Aunet, T. V. Cao, and A. Peiravi “Ultra Low Power Full Adder Topologies,” IEEE International Symposium on Circuits and Systems, pp. 3158-3161, May 2009
• H. Mahmoodi and A. Jalali, “Virtual Age: Enabling Technologies and Trends,” International Conference on Information Technology: New Generations, pp. 999-1004, April 2009
• F. Moradi, D. T. Wisland, H. Mahmoodi, A. Peiravi, S. Aunet, and T. V. Cao, “New Subthreshold Design Concepts in 65nm CMOS Technology,” IEEE International Symposium on Quality Electronic Design, pp. 162-166, Mar. 2009
• F. Moradi, D. T. Wisland, T. V. Cao, A. Peiravi, and H. Mahmoodi “1-Bit Sub Threshold Full Adder in 65nm CMOS Technology” Accepted for International Conference on Microelectronics, Dec. 2008
• A. Jalali and H. Mahmoodi, “Virtual Age: Next Wave of Change in Society,” International Conference on e-Commerce, e-Administration, e-Society, and e-Education, pp. 1593-1605, Jan. 2009
• F. Moradi, D. T. Wisland, S. Aunet, H. Mahmoodi, T. V. Cao, “65nm Sub-Threshold 11T-SRAM for Ultra Low Voltage Applications,” IEEE International Systems-On-Chip Conference, pp. 113-118, Sep. 2008
• F. Moradi, D. T. Wisland, H. Mahmoodi, T. V. Cao, “High Speed and Leakage-Tolerant Domino Circuits for High Fan-in Applications in 70nm CMOS Technology,” International Caribbean Conference on Device, Circuits, and Systems, pp.1-5, April 2008
• F. Moradi, H. Mahmoodi, and H. Alimohammadi, “A Leakage-tolerant CMOS Comparator in Ultra Deep Submicron CMOS Technology,” XXII Conference on Design of Circuits and Integrated Systems, pp. 415-418, Nov. 2007
• S. Paul, S. Bhunia, and H. Mahmoodi, “Low-Overhead Design Technique for Calibration of Maximum Frequency at Multiple Operating Points,” IEEE International Conference on Computer Aided Design, pp. 401-404, Nov. 2007
• K. Kim, H. Mahmoodi, and K. Roy, “A Low-Power SRAM Using Bit-Line Charge-Recycling Technique,” International Symposium on Low Power Electronic Design, pp. 177 – 182, Aug. 2007
• V. Tirumalashetty and H. Mahmoodi, “Clock Gating and Negative Edge Triggering for Energy Recovery Clock,” IEEE International Symposium on Circuits and Systems, pp. 1141-1144, May 2007
• Rajani Kuchipudi and Hamid Mahmoodi, “Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS,” IEEE International Symposium on Quality Electronic Design, pp. 27-32, Mar. 2007
• J. Yeung and H. Mahmoodi, “Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies,” IEEE International Systems-On-Chip Conference, pp. 261-264, Sep. 2006
• F. Moradi, A. Peiravi, and H. Mahmoodi “A Novel Leakage-Tolerant Domino Logic Circuit with Feedback from Footer Transistor in Ultra Deep Submicron CMOS,” IEEE International Conference on Mixed Design of Integrated Circuits and Systems, pp. 210-213, June 2006
• S. Mukhopadhyay, K. Kim, H. Mahmoodi, A. Datta, D. Park, and K. Roy, “Self-Repairing SRAM for Reducing parametric Failures in Nanoscaled Memory,” Symposium on VLSI Circuits, pp. 132-133, June. 2006
• N. Banerjee, S. Bhunia, H. Mahmoodi, and K. Roy, “Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating” Design, Automation, and Test in Europe, vol. 1, pp. 1 – 6, Mar. 2006
• K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, and T. Cakici, “Double-Gate SOI Devices for Low-Power and High-Performance Applications,” International Conference on VLSI Design, pp. 8, Jan. 2006
• A. Goel, S. Bhunia, H. Mahmoodi, and K. Roy, “Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability,” Asia and South Pacific Design Automation Conference, pp. 6, Jan. 2006
• K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, and T. Cakici, “Double-Gate SOI Devices for Low-Power and High-Performance Applications,” IEEE/ACM International Conference on Computer Aided Design, pp. 217-224, Nov. 2005
• S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, and K. Roy, “Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM,” IEEE Asian Test Symposium, pp. 176-181, Dec. 2005
• T. Cakici, H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Independent Gate Skewed Logic in Double-Gate SOI Technology,” IEEE International SOI Conference, pp. 83-84, Oct. 2005
• N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy, "Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis," IEEE International Conference on Computer Design, pp. 206-211, Oct. 2005
• S. Mukhopadhayay, K. Kang, H. Mahmoodi, and K. Roy, “Reliable and Self-Repairing SRAM in Nano-scale Technologies using Leakage and Delay Monitoring,” International Test Conference, pp. 10, Nov. 2005
• M. Meterelliyoz, H. Mahmoodi, and K. Roy, “A Leakage Control System for Thermal Stability During Burn-In Test,” International Test Conference, pp. 10, Nov. 2005
• Q. Chen, S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Process Variation Tolerant Online Current Monitor for Fault Immune Systems,” IEEE International On-Line Testing Symposium, pp. 171-176, July 2005
• S. Bhunia, N. Banerjee, Q. Chen, H. Mahmoodi, and K. Roy, “A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating,” Design Automation Conference, pp. 479-484, June 2005
• M. Cooke, H. Mahmoodi, Q. Chen, and K. Roy, “Energy Recovery Clocked Dynamic Logic,” Great Lake Symposium on VLSI, pp. 468 – 471, Apr. 2005
• F. Moradi, H. Mahmoodi, and A. Peiravi “A High Speed and Leakage-Tolerant Domino Logic for High Fan-in Gates,” Great Lake Symposium on VLSI, pp. 478-481, Apr. 2005
• A. Ghadiri and H. Mahmoodi, “Pre-capturing Static Pulsed Flip-Flops,” IEEE International Symposium on Circuits and Systems, pp. 2421-2424, May 2005
• Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, “Modeling and Testing of SRAM for New Failure Mechanisms due to Process Variations in Nanoscale CMOS,” IEEE VLSI Test Symposium, pp. 292-297, May 2005
• S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, “A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application,” Design, Automation, and Test in Europe, pp. 1136-1141, Mar. 2005
• S. Bhunia, H. Mahmoodi, and K. Roy, “Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning,” IEEE International Symposium on Quality Electronic Design, pp. 453-458, Mar. 2005
• S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Design of High Performance Sense Amplifier Using Independent Gate Control in Sub-50nm Double-Gate MOSFET," IEEE International Symposium on Quality Electronic Design, pp. 490-495, Mar. 2005
• F. Moradi, A. Peiravi, and H. Mahmoodi, “A New Leakage-Tolerant Design for High Fan-in Domino Circuits,” International Conference on Microelectronics, pp. 493-496, Dec. 2004
• A. Ghadiri and H. Mahmoodi, “Dual-Edge Triggered Static Pulsed Flip-Flops,” International Conference on VLSI Design, pp. 846-849, Jan. 2005
• S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Statistical Design and Optimization of SRAM Cell for Yield Enhancement," International Conference on Computer Aided Design, pp. 10-13, Nov. 2004
• H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "Estimation of Delay Variations Due to Random-Dopant Fluctuations in Nanoscaled CMOS Circuits," IEEE Custom Integrated Circuits Conference, pp. 17-20, Oct. 2004
• H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "High Performance and Low Power Domino Logic Using Independent Gate Control in Double-Gate SOI MOSFETs," IEEE International SOI Conference, pp. 67-68, Oct. 2004
• S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, "A Novel Low-Power Scan Design Technique Using Supply Gating," IEEE International Conference on Computer Design, pp. 60-65, Oct. 2004 (Best paper award)
• S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, "First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 314-315, Oct. 2004
• S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling and Estimation of Failure Probability due to Parameter Variations in Nanoscale SRAMs for Yield Enhancement," Symposium on VLSI Circuits, pp. 64-67, June 2004
• H. Mahmoodi and K. Roy, “Data-Retention Flip-Flops for Power-Down Applications,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 677-680, May 2004
• H. Mahmoodi and K. Roy, “Dual-Edge Triggered Level Converting Flip-Flops,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 661-664, May 2004
• Y. Wang, H. Mahmoodi, L. Chiou, H. Choo, J. Park, W. Jeong, and K. Roy “Hardware Architecture and VLSI Implementation of a Low-Power High-Performance Polyphase Channelizer with Applications to Subband Adaptive Filtering,” International Conference on Acoustics, Speech, and Signal Processing, vol. 5, pp. 97-100, May 2004
• A. Ghadiri and H. Mahmoodi, “Comparative Energy and Delay of Energy Recovery and Square Wave Clock flip-Flops for High-Performance and Low-Power Applications,” International Conference on Microelectronics, pp. 89–92, Dec. 2003
• H. Mahmoodi and K. Roy, “A Leakage-Tolerant High Fan-in Dynamic Circuit Design Style,” IEEE International Systems-On-Chip Conference, pp. 117-120, Sep. 2003
• M. Cooke, H. Mahmoodi, and K. Roy, “Energy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications,” International Symposium on Low Power Electronic Design, pp. 54-59, Aug. 2003
• K. Roy, H. Mahmoodi, S. Mukhopadhyay, “Leakage control for Deep Submicron Circuits,” SPIE's First International Symposium on Microtechnologies for the New Millennium, vol. 5117, pp. 135-146, May 2003
• S. Mukhopadhyay, H. Mahmoodi, C. Neau, K. Roy, “Leakage in Nanometer Scale CMOS Circuits,” International Symposium on VLSI Technology, Systems, and Applications, pp. 307–312, Apr. 2003
• H. Mahmoodi and K. Roy, “Self-precharging flip-flop (SPFF): a new level converting flip-flop,” European Solid-State Circuits Conference, pp. 407-410, Sep. 2002
• J. Park, W. Jeong, H. Choo, H. Mahmoodi, Y. Wang, and K. Roy “High performance and low power FIR filter design based on sharing multiplication,” International Symposium on Low Power Electronic Design, pp. 295–300, Aug. 2002
• H. Mahmoodi and A. Afzali-Kusha, "Efficient Power Clock generation for Adiabatic Logic", IEEE International Symposium on Circuits and Systems, vol. 4, pp. 642-645, May 2001
• H. Mahmoodi and A. Afzali-Kusha, "Low-Power Low-Noise Adder Design with Pass-transistor Adiabatic Logic", International Conference on Microelectronics, pp. 61–64, Nov. 2000
• H. Mahmoodi, A. Afzali-Kusha and M. Nourani, "Efficiency of Adiabatic Logic for Low-Power, Low-Noise VLSI", IEEE Midwest Symposium on Circuits and Systems, vol. 1, pp. 324-327, Aug. 2000

• Apparatus and Methods for Determining Memory Device Faults, Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,548,473 on June 16, 2009 (Received Inventor Recognition Award by SRC)
• Self Repairing Technique in Nano-Scale SRAM to Reduce Parametric Failures, S. Mukhopadhyay, H. Mahmoodi, K. Kim, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,508,697 on Mar. 24, 2009 (Received Inventor Recognition Award by SRC)
• Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating, S. Bhunia, N. Banerjee, H. Mahmoodi, Q. Chen, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,454,738 on Nov. 18, 2008
• Low Power Scan Design and Delay Fault Testing Technique Using First Level Supply Gating, S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,319,343 on Jan. 15, 2008
• Sense Amplifier Circuit, S. Mukhopadhyay, H. Mahmoodi, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,304,903 on Dec. 4, 2007

• A. Jalali and H. Mahmoodi, "Programmable Logic Controllers: Principles and Applications", Tehran: Iran University of Science and Technology Press, 1999 (Translation: Awarded the best translated book of the year by Iran Ministry of Culture in 2001)

• N. Morrison and H. Mahmoodi, "Keeping Technology Cool", College of Science and Engineering Inter-science Magazine, pp.42-44, Dec 2008
• H. Mahmoodi "LOW POWER, ROBUST, AND HIGH PERFORMANCE CIRCUIT DESIGN IN NANO-SCALE CMOS," PhD Dissertation, Purdue University, Aug. 2005
• K. Roy, H. Mahmoodi, and S. Mukhopadhyay, “Leakage Current in Scaled CMOS: Mechanisms and Reduction Techniques,” the SRC Cavin's Corner, http://www.src.org, Aug. 2003
• H. Mahmoodi “Low-Power Design of Digital Systems Based on Adiabatic Switching Principles,” M.S. Thesis, University of Tehran, Sep. 2000

Professional Associations ::

• Technical program committee member of International Symposium on Quality Electronic Design (ISQED), 2006-present
• Technical program committee member of International Symposium on Low Power Electronics and Design (ISLPED), 2009-present
• Technical program committee member of IEEE Custom Integrated Circuit Conference (CICC), 2005-2008
• Graduate Faculty of Purdue University, Dec. 2005-present
• Member of Institute of Electrical and Electronics Engineers (IEEE)
• Executive committee member of IEEE San Francisco Section, 2007-2008

last updated: 12/18/2009