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jump to page contentHamid Mahmoodi

Nano-Electronics and Computing Research Laboratory

School of Engineering

College of Science and Engineering

San Francisco State University

Welcome!

Research :: Courses :: Papers and Publications :: Professional Associations :: CV

Contact Information

Title:

Professor

Program:

Electrical and Computer Engineering

E-mail:

mahmoodi@sfsu.edu

Office Phone:

(415) 338-6579

Fax:

(415) 338-0525

Mailing Address:

School of Engineering
San Francisco State University
1600 Holloway Avenue
San Francisco, CA 94132


Research Interests ::

  • Design solutions for emerging nanotechnologies
  • Design for reliability in nano-scale technologies
  • Low-power, robust, and high-performance design in nano-scale technologies
  • Low-power VLSI testing and design for testability
  • Very Large Scale Integrated (VLSI) circuits and systems

Visit Nano-electronics and Computing Research Laboratory (NeCRL) for more details.

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Courses ::

  • ENGR 856: Nano-Scale Circuits and Systems
  • ENGR 852: Advanced Digital Design
  • ENGR 850: Digital Design Verification
  • ENGR 848: Digital VLSI Design
  • ENGR 844: Embedded Systems
  • ENGR 453: Digital Integrated Circuit Design
  • ENGR 478: Design with Microprocessors
  • ENGR 378: Digital System Design
  • ENGR 356: Digital Design
  • ENGR 212: Introduction to Unix/Linux for Engineers
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Papers and Publications ::

IEEE has copyright on papers published in IEEE journals and conferences. IEEE papers are available in IEEE Xplore Digital Library.

Refereed Journal Papers:

Refereed Conference Papers:

Patents:
  • Apparatus and Methods for Determining Memory Device Faults, Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,548,473 on June 16, 2009 (Received Inventor Recognition Award by SRC)
  • Self Repairing Technique in Nano-Scale SRAM to Reduce Parametric Failures, S. Mukhopadhyay, H. Mahmoodi, K. Kim, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,508,697 on Mar. 24, 2009 (Received Inventor Recognition Award by SRC)
  • Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating, S. Bhunia, N. Banerjee, H. Mahmoodi, Q. Chen, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,454,738 on Nov. 18, 2008
  • Low Power Scan Design and Delay Fault Testing Technique Using First Level Supply Gating, S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,319,343 on Jan. 15, 2008
  • Sense Amplifier Circuit, S. Mukhopadhyay, H. Mahmoodi, and K. Roy, Patent issued by the US Patent and Trademark Office under Patent No. 7,304,903 on Dec. 4, 2007
Books and Book Chapters:
  • H. Mahmoodi, “Low-Power and Variation-Tolerant Memory Design”, In: S. Bhunia and S. Mukhopadhyay, Low-Power Variation-Tolerant Design in Nanometer Silicon (ISBN: 978-1-4419-7418-1), Chapter 5, pp. 151-183, Springer, 2011
  • A. Jalali and H. Mahmoodi, "Programmable Logic Controllers: Principles and Applications", Tehran: Iran University of Science and Technology Press, 1999 (Translation: Awarded the best translated book of the year by Iran Ministry of Culture in 2001)
Miscellaneous:
  • N. Morrison and H. Mahmoodi, "Keeping Technology Cool", College of Science and Engineering Inter-science Magazine, pp.42-44, Dec 2008
  • H. Mahmoodi "LOW POWER, ROBUST, AND HIGH PERFORMANCE CIRCUIT DESIGN IN NANO-SCALE CMOS," PhD Dissertation, Purdue University, Aug. 2005
  • K. Roy, H. Mahmoodi, and S. Mukhopadhyay, “Leakage Current in Scaled CMOS: Mechanisms and Reduction Techniques,” the SRC Cavin's Corner, http://www.src.org, Aug. 2003
  • H. Mahmoodi “Low-Power Design of Digital Systems Based on Adiabatic Switching Principles,” M.S. Thesis, University of Tehran, Sep. 2000

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Professional Associations ::

 

last updated: 09/21/2016

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